This invention relates to a bipolar memory circuit which has current switching type memory cells.
In the bipolar memory circuit having the current switching type memory cells, the distinction between the read cycle and write cycle of information is determined in accordance with the level of a write enabling signal which is externally supplied.
The bipolar memory circuit can therefore cause a malfunction in response to the interference of a noise in the write enabling signal in, for example, a read cycle period.
In order to prevent the bipolar memory circuit from erroneously operating in response to the noise etc., a method wherein a write enabling signal and a signal obtained by delaying the write enabling signal are logically combined and the resulting composite signal is used as an input signal to a write driver circuit has been proposed as disclosed in Japanese patent application Laid-open Publication which was published on Mar. 18, 1977, No. 52-35535. According to this method, any pulse noise to interfere in the write enabling signal as has a pulse width less than the signal delay time becomes negligible.
With the known method, however, the setup time becomes longer by the delay time of the signal. Moreover, since the write time in the signal obtained by the logic combination decreases, the pulse width of the write enabling signal to be externally supplied must be increased. With the known method, accordingly, the write cycle period lengthens.